K4H561638F-UCCC Datasheet, Samsung semiconductor

* 200MHz Clock, 400Mbps data rate.
* VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirec.

DDR SDRAM 16Mb x 16 32Mb x 8 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS C.